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STM32 TIMERS #7. Cascading Timers || External Clock mode || Reset Mode
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Jan 14, 2023
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View Video Transcript
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foreign
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[Music]
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Tech
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[Music]
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this is the seventh video in the SDM 32
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timer series and today we will continue
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with another application of the timer
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synchronization
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we will see how to Cascade the timers in
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series and by doing this we can combine
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three 16-bit timers into a 48-bit timer
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basically in Cascade the frequency of
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one timer will be used as the clock for
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another timer
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this can be achieved by using the update
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event as the master timer output signal
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along with external clock mode for the
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slave timer
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the video was going to be very long so I
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have decided to split them into two
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parts
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this video will basically cover the
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slave timer in the external clock mode
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also we will see the reset mode towards
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the end of the video
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and in the next video we will make a
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48-bit counter using three timers and we
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will also see its application
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so let's start the cube IDE and create a
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new project
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I am using the stm32f446re
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give some name to the project and click
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finish
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first of all I am selecting the external
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Crystal to provide the clock to the MCU
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the board has 8 megahertz Crystal and I
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want to run the controller at 90
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megahertz
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I am choosing 90 megahertz because I
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want all the timers to have the same
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clock speed and apb2 timer clock can run
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at a maximum of 90 megahertz
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the clock setup is done so let's start
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setting the timers now
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timer 1 is going to be the master timer
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here I am enabling the pwm on Channel 1
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so that we can see the output of timer
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1.
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right now the timer clock is at 90
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megahertz so the prescaler of 90 would
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bring the clock down to 1 megahertz
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the auto reload of 100 would further
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reduce the timer frequency to 10
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kilohertz
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the trigger event should be selected as
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the update event
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basically when the counter will reach
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the auto reload value of 100 this update
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event will get triggered
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and if we use the update event in
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combination with the external clock mode
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or gated mode the output frequency of
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this timer can be used as the clock for
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the slave timer
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since the auto reload is 100 if I keep
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the pulse at 40 there will be the pwm
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signal with 40 duty cycle
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let's quickly see what we have
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configured so far
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the timer one output frequency will be
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APB timer clock divided by the prescaler
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times the auto reload value and this
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will be equal to 10 kilohertz
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now we will configure the timer too
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let's see the internal trigger
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connection diagram
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you can find it in the reference Manual
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of your controller
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here you can see the timer 2 can be a
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slave to timer 1 and it will be
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triggered by the ITR 0.
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similarly the timer 3 can be triggered
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by the timer 2 via the itr1 signal
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let's configure the timer 2 now
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the slave mode will be the external
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clock mode and the trigger Source will
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be itr0
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I am selecting the pwm on Channel 1 so
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that we can see the output of this timer
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now as I mentioned when the update event
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is used with a combination of the
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external clock mode the timer one's
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output frequency will act as the input
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clock for the timer too
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timer 2's frequency will be equal to
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input clock divided by the prescaler
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times the auto reload
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the timer 1 frequency is 10 kilohertz
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and if we use the prescaler 1 and auto
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reload of 100 the timer 2's frequency
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will be 100 Hertz
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so let's configure the prescaler as one
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and the auto reload is 100.
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I am keeping the pulse at 40 so the pwm
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duty cycle will be 40 percent
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this timer 2 is a slave to timer 1 and
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master to time of three
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so we also need to enable the trigger
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event selection as the update event
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now the timer 3 will also have the
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similar configuration except that the
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trigger sources from timer 2 so I tr1
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timer 3 frequency will be calculated in
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the similar Manner and if I use the auto
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reload of 10 the frequency will be 10
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Hertz
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now since the auto reload is set to 10 I
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am keeping the pulse at 4 so that we
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could get the duty cycle of 40 percent
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now all three timers are set with timer
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1 running at 10 kilohertz timer 2 at 100
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Hertz and timer 3 at 10 Hertz
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click save to generate the code
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there is not much to do in the
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programming part we will just start the
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pwm for all three timers
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all right let's build and Flash the code
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to the board
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I have connected the pwm pins to the
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logic analyzer
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here we are getting the output from each
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timer
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let's analyze it now
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here you can see the timer one with 10
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kilohertz frequency and 40 duty cycle
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the timer 2 is running at 100 Hertz with
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40 Duty
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and timer 3 is at 10 Hertz with 40 Duty
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this is as per the calculations we did
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earlier
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so we saw how the frequency of one timer
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can be used as the clock for the second
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timer
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using this we will Cascade three timers
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and make a 48-bit counter so that we can
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read a wide range of frequencies
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this will be covered in the next video
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let's take a look at the reset mode now
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here I have already configured the
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timers
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I have disabled timer 1 and timer 2 is
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now in the master mode with pwm enabled
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on Channel 1. it is being clocked by the
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APB clock so the base frequency is at 90
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megahertz
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the auto reload value of 10 000 will
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reduce the clock to 9 kilohertz
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also I am keeping the duty at 40 so with
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the auto reload value being 10 000 this
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is equivalent to 0.4 percent
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here is the calculation for the timer 2
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output frequency
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also the trigger event is set to update
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event
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now the timer 3 is the slave to timer 2
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and is being used in the reset mode
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in reset mode whenever the update event
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is triggered it will reset the counter
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of the slave timer
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the trigger signal is coming from timer
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2 so it is set to itr1
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as I mentioned when the update event is
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used with the reset mode or trigger mode
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all the timers will be clocked by the
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APB clock unlike the previous case where
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the frequency of the master timer served
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as the clock for the slave timer
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here I have set the auto reload of 1234.
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the timer clock was 90 megahertz and now
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it is around 73 kilohertz
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the pulse is set to 300 which is
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approximately 24 of the auto reload
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value
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this is it for the setup click save to
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generate the code
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the code will remain the same just
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comment out the timer 1 as it is not
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being used
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let's build and Flash the code
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here we are getting the pwm output for
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both the timers
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you can see the timer 2 has the
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frequency of 9 kilohertz and duty is
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around 0.4 percent
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timer 3 has the frequency of around 73
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kilohertz with the duty around 24
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percent
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let's zoom in to understand what's
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happening
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if you check the width of the timer 3
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signal it is around 3 or 3.5
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microseconds
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the data is a little bit inconsistent
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because I can't use higher sampling rate
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with this logic analyzer
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but this is enough for us to understand
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how reset mode works
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so the width is either 3 or 3.5
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microseconds except at this point
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here it is 5 microseconds
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so what happened here
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if you have seen my pwm video or
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previous timer videos you would know
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that this is the point where the
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Overflow occurs in the timer too
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when this happens an update event gets
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triggered and the counter of timer 3
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resets at this point
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basically here the counter of timer 3
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overflowed and then it started counting
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up while doing so another reset signal
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came and the counter resets back to zero
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and again starts counting up if you
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measure the time from here till the
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signal goes low it will be approximately
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the same as the others
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this 3.5 microseconds is the actual
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width of this pwm signal
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we can calculate the similar thing at
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any other point and it will give us the
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time equal to the width of the signal
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so you saw how the reset mode is used to
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reset the counter of the slave timer
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in this case the trigger Source was used
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as the itr1 so the timer 2 was
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responsible for this reset
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but you can also use some external
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signal to do this reset
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we will see that in the upcoming videos
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one more thing you notice that when
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using the trigger mode the APB clock was
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used as the timer clock
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but if I switch it to the external clock
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mode now the timer 2's frequency will be
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used as the clock for timer 3.
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let's quickly see the output of this
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here you can see the frequency has been
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reduced significantly this is because
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now 9 kilohertz is being used as the
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input clock rather than 90 megahertz in
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the reset mode
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so I hope this video was able to explain
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the difference between the external
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clock mode and the reset mode
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in the next video we will use the
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external clock mode and using that we
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will create a 48-bit counter which will
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then measure frequencies with larger
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bandwidth
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this is it for this video
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the link to download the code is in the
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description
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leave comments in case of any doubt
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keep watching and have a nice day ahead
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foreign
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[Music]