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STM32 MPU Config || #5. MPU Sub-Region setting
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Jul 8, 2021
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View Video Transcript
0:01
[Music]
0:10
welcome to the fifth video in the mpu
0:12
configuration
0:14
this video is in the continuation from
0:16
the last one
0:17
and today we will see how to use the
0:19
sub-regions in the mpu
0:23
this is the picture from one of the sds
0:26
video and it shows how the region is
0:28
divided
0:30
a region can be divided to eight
0:31
sub-regions
0:33
only if the region size is greater than
0:35
256 bytes
0:38
another important point is that the
0:40
setting a corresponding sub-region bit
0:42
will exclude the sub region from the mpu
0:45
region
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for example if we have this 8 kilobytes
0:48
region in the mpu
0:51
if we are using sub region then this 8
0:53
kilobytes region will be divided into 8
0:56
subparts
0:58
this means each subpart will be one
1:00
kilobyte in size
1:02
now if the subregion setting is zero
1:05
cross three a
1:06
then all the positions that are set to
1:08
one will not be a part of the mpu
1:10
configuration
1:12
this region will exhibit the default
1:14
memory behavior
1:16
and all the positions that are set to
1:18
zero will be a part of
1:19
mpu configuration we will see the
1:23
working of this
1:27
here i have already created a project so
1:30
i will directly take you to the qmx
1:38
configuration
1:42
here the clock is set as usual in the
1:45
mpu configuration
1:47
i have selected the background region
1:49
privileged access
1:51
the base address is set to 3 million
1:54
this is actually the address of one of
1:56
the srams
1:58
i am also using the 8 kilobyte size
2:02
let's disable the sub-regions at first
2:04
so it will be easier to compare when we
2:06
enable it
2:10
all access are permitted and the region
2:13
is set as shareable
2:14
and non-cachable
2:24
i am also using adma just like the
2:27
previous video
2:47
here we have 2 buffers each 10 bytes in
2:50
size
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and they are defined at some particular
2:52
locations in the memory
3:04
here the copy buffer is located at the
3:06
start of the sram
3:07
and the paste buffer is located at an
3:09
offset of 1 kilobyte from the start of
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the sram
3:13
let's build it once
3:27
you can also see the buffers in the
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memory details
3:36
here is the c data at the start of the
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sram
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and the p data is at 400 offset
3:48
i have created a callback for the dma
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and this flag will be set
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when the data transfer is finished
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here i am registering the callback for
4:01
the dma
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memory to memory transfer dma don't have
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the callbacks
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so we need to register manually this
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parameter here defines
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when the callback will be called this
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you can find in the dma.h file
4:20
this is the id for the full transfer
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and at last we have the callback itself
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now in the while loop we will first set
4:34
the data in the c data buffer
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then start the dma to transfer this data
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here c data is the source and p data is
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the destination
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then we will wait for the transfer
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complete flag to set in the callback
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and we will repeat the process again as
4:54
for now we have made this region
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non-cachable so this transfer should
4:58
work
4:59
before we run this let me show you how
5:02
the region is set right now
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here is the setting for the region
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even if we consider that the region is
5:15
divided into eight subparts
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here all the subparts are set to zero
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and everything will be included in the
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mpu region
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let's see the working now
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here are both the buffers in the live
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expression
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let's run it
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so everything seems to be working all
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right
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both the data buffers have the same data
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so no coherency issue
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this is working because we set the 8
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kilobytes of non-cacheable region in the
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mpu
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and both the buffers are placed in that
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region
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now let's go back to the q m x and
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configure the sub regions
6:11
right now every region is included in
6:13
the mpu
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and we will exclude the p data from it
6:18
to do that we need to set a one in the
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second position
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and that means we need to write zero
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cross zero two
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in the mpu sub region settings
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everything else will remain unchanged
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and we will just exclude the p data
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region from the mpu configuration
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this means the p data region will
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exhibit the default memory behavior
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where it is a cachable region let's
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see what happens with this configuration
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we will keep our program same as before
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and run it
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so everything is working fine here also
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let's understand what's going on
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remember that we have only excluded the
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p
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data region but the c data region is
7:26
still non cachable
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so the cpu writes the data to this
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region and since the region is
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non-cacheable
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the dma is able to copy the latest data
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from it
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that's why we see the same data in the
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p-data buffer also
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but if we make the c data region
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cacheable the coherency issues should
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start
7:54
to do that we will set the region
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setting to zero cross zero
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one this will exclude the c
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data region from the mpu and this region
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will say to the default behavior
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which will make it cacheable
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let's test it
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now the p data region is not updating
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this is because the c data region is
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cacheable and the dmas keep fetching the
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cached data
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which was the initial data in the buffer
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this was explained in the previous video
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and is also known as data coherency
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issue
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so we saw even the region was set to
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non-cacheable
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but with the sub-region configuration
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the c data becomes cachable
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and we had to face the coherency issue
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now let's see what happens if we change
9:01
the location of the c data buffer
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here i am going to put the c data in
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some other location
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which is set to zero in the sub region
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settings
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c hundred would be fine so if we put the
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c
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data buffer at this new location it
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should follow the mpu configuration
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and the buffer should be non-cacheable
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let's make the changes in the location
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of the c
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data buffer
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here i am updating the location in the
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flash script
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so we have some error
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here it's mentioned that the memory
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counter cannot go backwards
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well this is happening because we have
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defined the higher location before the
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lower one
10:00
we need to define the locations in their
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increasing order
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now it builds up successfully all right
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let's see the working now
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as expected now the dma works perfectly
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it's able to copy the newest data from
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the c data buffer
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because the c data buffer is in the
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non-cachable region now
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remember that only the first sub-region
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was excluded from the mpu
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so if the c data is placed in that
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region it will follow the default
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properties of that memory region
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but now we have changed the location of
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c data buffer
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so it is following the properties of the
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mpu settings we did
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this is it for this video i hope
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things didn't got too complicated
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you can ask the doubts in the comment
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section
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this is the last video i have planned
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for the mpu configuration
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but if something new comes up i will
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make another video
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this is it for now keep watching
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be safe and have a nice day ahead