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STM32 MPU Config || #4. CubeMX Setup
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Jul 3, 2021
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View Video Transcript
0:03
[Music]
0:09
welcome to controllers tech
0:11
in the previous video we saw the data
0:14
coherency issue
0:15
and how to resolve it this video will
0:18
show an actual working example of what
0:20
we saw in the previous video
0:23
also we will see how to configure the
0:25
mpu in the cube mx let me show you the
0:30
configuration first
0:34
here i have enabled the instruction
0:37
cache and the data cache
0:39
other than that everything is set to
0:42
default setup
0:49
here i have created two buffers receive
0:52
and transmit
0:54
and both of them have been assigned a
0:56
particular location in the memory
1:03
here is the assignment they are both
1:06
placed in the sram one
1:11
i am doing this because the ram in my
1:13
case starts from dtcm region
1:16
and it's not cacheable therefore the
1:19
demonstration will not be valid in this
1:21
region
1:22
you can watch the memory management
1:24
video to understand this
1:27
check it in the cortex m7 playlist
1:30
let's see example from the previous
1:33
video
1:38
we talked about two different coherency
1:41
issues
1:42
first when dma writes to sram
1:46
and second when dma reads from sram
1:59
i am using a memory to memory transfer
2:01
for the dma
2:25
so first we will write some data to the
2:27
tx buffer
2:29
and then we will use the cpu to copy the
2:32
data from the tx buffer to the rx buffer
2:35
i am using the cpu transfer first
2:39
let's test this part to see if the
2:41
transfer works in the cachable region
2:44
here you can see the location of the tx
2:46
buffer and the rx buffer
2:54
they are just where we have allocated
2:56
them to be
3:20
here i have put both the buffers in the
3:22
live expression
3:33
so the transfer is working all right
3:36
the cpu can copy data around without any
3:39
issue
3:40
that's why the cases are very specific
3:43
to dma
3:48
now instead of mem copy let's try to use
3:51
the dma to transfer this data
3:54
here the source address is the tx buffer
3:57
and destination address is rx buffer
4:00
100 milliseconds will be enough to do
4:02
the transfer
4:04
abort the dma so that we can start it
4:07
again
4:10
all right let's run it
4:18
you can see the tx buffer is updating
4:20
but the rx buffer is not changing
4:24
this brings us to the issue we discussed
4:26
in the previous video
4:29
here both these issues are taking place
4:31
at the same time
4:33
because the dma is reading from the sram
4:36
that is tx buffer
4:38
and dma is writing to sram that is rx
4:41
buffer
4:42
let's start from the solution for the
4:44
dma reading from sram
4:56
here after the cpu writes the data to
4:59
the sram
5:00
we must perform a cache clean operation
5:02
which will flush the cached tx buffer
5:05
into the sram so after copying the data
5:08
into the tx buffer
5:10
we must clean cache by using clean d
5:12
cache by address
5:20
let's call the function here the address
5:23
will be the address of the tx buffer
5:25
and the size will be the size of the tx
5:36
buffer
5:46
now let's see for the dma writing to the
5:50
sram
5:57
after the dma is finished writing we
5:59
must invalidate the cache
6:06
we can do it in the transfer complete
6:08
callback
6:09
[Music]
6:16
i will just do it here for now
6:19
invalidate d
6:20
cash by address the address is the
6:22
address of the rx buffer
6:24
and the size is the size of the rx
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buffer
6:27
let's test it
6:32
all right the first set of data is
6:35
copied
6:38
the second set got copied too
6:47
it's working all right now so whenever
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we are using multiple masters
6:52
we must perform these steps before the
6:55
dma reads the data
6:57
we must perform cache clean
7:02
and the invalidate cache must follow
7:04
after the dma writes the data into the
7:06
sram
7:08
this was the software solution to
7:10
maintain coherency
7:12
if this seems too much for you there is
7:14
another way around it
7:16
and i personally prefer using the mpu to
7:19
solve the coherency issue
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so let's see the mpu configuration
7:42
first of all here we will select the
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third option
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mpu region privilege access only and mpu
7:49
disabled
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during hard fault
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now here we have bunch of settings for
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different regions
8:03
there are 16 regions for me but this
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might be different for you
8:07
we will start will the region zero
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let's enable it the first parameter
8:14
is the base address here we will put the
8:17
address of our buffers
8:23
the buffers are starting from this
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particular address
8:34
next is the region size
8:41
i have placed the buffers at different
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locations in the memory
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and together they take around 63 bytes
8:53
of space
8:53
from the beginning note that the buffer
8:56
size are 10
8:57
bytes each so they take 20 bytes
9:00
but since i have kept them at different
9:02
locations the region between them is
9:04
also covered in this 63 bytes
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so we will choose the next possible size
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and that is 64 bytes
9:17
this is the image i showed you in the
9:19
previous video
9:20
and this have the configuration settings
9:22
for different regions
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here we can choose the region type that
9:27
suits best
9:29
for example we can make the memory as
9:31
the shared device
9:32
where we can make it shareable and
9:34
bufferable or we can keep it as normal
9:37
but as a non-cachable memory i will go
9:40
with the shareable device type
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just to demonstrate that the normal
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memory can also be made to behave as a
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device type
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so the text field will be zero
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instruction should be disable
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as there are no instructions available
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here
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and make it shareable non-cacheable and
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bufferable
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this is as per the requirement mentioned
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here
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similarly if you want to set another
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memory region
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you can choose here and configure it as
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per the requirement
10:35
now since we have configured the mpu we
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don't need this software solutions
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let's just disable them and see if the
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dma can handle the transfer
11:07
you can see the rx buffer is updating
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just fine
11:11
so the dma is able to read and write to
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sram
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without any issue
11:21
i have shown you two different methods
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to handle the data coherency issues
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and you can choose according to your
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convenience
11:30
just to show you that it is working
11:32
because of the mpu configuration
11:34
let's disable the mpu config and see
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what happens
11:45
now the data is not updating in the rx
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buffer
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so configuring the region as a shared
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device made the dma transfer possible
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this is it for this video i hope you
11:57
understood the mpu configuration
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data coherency issue and how to solve it
12:06
this is the end for the mpu
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configuration series
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there is one more topic remaining which
12:13
is about the sub-regions in the mpu
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but we will skip it for now it's not
12:18
important
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unless you are writing a very
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complicated program
12:23
if required i will cover it in the
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future
12:26
since the memory regions are covered now
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i will cover some external memories
12:31
like sdram quad spi and i will also make
12:34
videos on ethernet peripheral
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that's it for today keep watching
12:41
and have a nice day ahead
13:03
you