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STM32 MPU Config || #2. Memory Types and Attributes
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Jul 2, 2021
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View Video Transcript
0:03
[Music]
0:09
hello everyone
0:11
welcome to the second video of mpu
0:14
configuration
0:15
this video will cover the memory types
0:18
and attribute types in cortex
0:20
m7 processors we will also see some
0:23
examples for the mpu configuration
0:26
let's start with the memory types the
0:30
cortex m7 memory is mainly divided into
0:33
three types
0:34
normal type device type and the strongly
0:38
ordered type
0:39
in the normal memory region the
0:41
processor can reorder the transactions
0:44
to perform the speculative reads
0:47
normal memory is mainly used for code
0:50
execution
0:51
and it allows the speculative access
0:54
all the rams are normal memory types
0:57
in the device memory type or the
0:59
strongly ordered memory type
1:01
the order of transactions are intact
1:04
which means the cpu can't reorder the
1:06
transactions
1:08
the device memory is bufferable and that
1:10
means
1:11
the right to memory can be buffered the
1:14
instruction execution may continue
1:16
and the right to memory can be done
1:18
later
1:20
microcontroller registers a typical
1:22
example of device type
1:23
memory regions on the other hand
1:27
in the strongly ordered memory type the
1:29
write is not bufferable
1:31
so the next instruction can only execute
1:33
once the previous instruction have
1:35
finished writing the data
1:38
external nand memories are typical
1:40
example of strongly ordered memory types
1:42
since they're each right needs to be
1:44
visible to the memory
1:46
here you can see the default memory
1:48
types in cortex m7 processors
1:52
you can pause the video and read about
1:54
them
1:56
or i will leave the link to this
1:57
presentation in the description below
2:01
basically the ram region is normal
2:03
memory type
2:05
the peripherals and the external devices
2:08
are the device memory types
2:10
and the system specific controls like
2:13
interrupt vectors
2:14
and timers are strongly ordered memory
2:17
types
2:18
even though the memory regions have
2:20
these properties by default
2:22
we can modify them according to our
2:24
application
2:26
and this is where the m p u comes into
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picture
2:30
we will see more about them in a while
2:33
there are mainly 4 attributes in the
2:35
cortex m7
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shareable cachable bufferable and
2:40
execute never
2:42
a shareable region must be used when the
2:45
multiple masters are accessing a memory
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region
2:49
example dma and processor core trying to
2:53
access the same region
2:55
or maybe 2 dma are using the same region
2:59
strongly ordered memory types are always
3:02
shareable
3:03
also if the region is both shareable and
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cachable
3:07
then the data cache can't be used in
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that region
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and only the instruction cache can be
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used
3:14
a typical example for shareable region
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usage is in the ethernet
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here the transmit and receive dma
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descriptors are going to share the
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common region
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so this is how we set the 256 bytes of
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shareable region
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we will see more about this in the
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ethernet tutorials
3:35
next we have is the cachable attribute
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this is the region where the instruction
3:40
and data cache can be used
3:43
using cache improves the performance by
3:45
a significant amount
3:46
but the problem occurs when multiple
3:48
masters access the same region
3:51
here the data synchronization cannot be
3:54
done with cache enabled
3:56
we have already covered this in previous
3:58
video that when multiple masters access
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some common region the cache must be
4:03
disabled
4:04
or we can also try some software
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solution where we invalidate the cache
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or clean the cache anyway i will go with
4:12
disabling the cachable region
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and here is an example for the same
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suppose the rx buffer is at this
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location and
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dma is trying to copy the data from the
4:23
peripheral to this rx buffer
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in this case we must disable the cache
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for this region
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and we can do that in the mpu i will
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cover the reason for this in the next
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video
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where we will just focus on cache
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policies
4:39
next is the bufferable attribute in the
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bufferable region
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the right to the memory can be buffered
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this means that the instruction may
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continue to execute
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while the write can be performed later
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device memory regions are bufferable
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like the microcontroller registers
4:58
next is the execute never attribute
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this is again a very important attribute
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and it should be set
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where we don't want the instructions to
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execute from
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the instructions are stored and executed
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from the ram
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which is typically a normal memory
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region
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so the device memory region and the
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strongly ordered memory regions should
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be set as execute never attribute
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we can again take a look at the default
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memory attributes
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and here you can see everything other
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than normal memory region
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is set to execute never this is an
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example
5:34
where the flash have been relocated to
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the qspr
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you might have heard of booting from the
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external memory
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and this is what's going on here the
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qspi by default is set to external ram
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as a normal memory type this means that
5:52
the instructions can execute from this
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region
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and this would make the processor to
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perform speculative instruction fetch in
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this region
6:00
but since we are using it as a flash
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memory we must prevent the instruction
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fetching from this
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region and that's why we would set it as
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execute never region
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here are some important thing that
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should be kept in mind
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these are the instructions from one of
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the sds documents
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for any address that is not safe to
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access
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speculative access must be prevented
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to do that we can set the region as
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device
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or strongly ordered memory along with
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the execute never
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and finally here is the list of
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attributes set up for the different
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types of memory
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for example if we want to set the memory
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as shared device
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we have to set the tech zero
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non-cachable but bufferable and
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shareable
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this way we can set the desired memory
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region
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using the attributes in the mpu
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this is it for this video we saw the
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memory types and attribute types in
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cortex
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m7 processors and also some examples of
7:04
how to use these
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attributes the next video will cover the
7:08
data coherency
7:10
and the cache policy you can download
7:13
the presentation below keep watching
7:17
and have a nice day ahead
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