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welcome to controllers tech this is the
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first video in the series
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where we will be discussing about memory
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there will be few more videos on this
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topic and they all will be mostly the
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as due to the lack of proper resources i
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have put together few conclusions from
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and i will share them with you if
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something you think is lacking
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let me know in the comments i will put
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and release another video so let's start
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with the first one today
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and here we will see what is mpu and why
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memory protection unit is a piece of
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hardware which is attached to the mcu
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itself the main purpose of mpu is to
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prevent any process from accessing the
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that hasn't been assigned to it it does
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that by allowing the privileged access
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for the process in the allocated
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privileged access means that the process
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can use all the instructions
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and have access to all the resources the
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memory protection unit monitors all the
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including the instruction fetching and
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any violation of the access by the
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process will trigger fault exception
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this could result in unpredictable
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behavior and sometimes hard
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fault too we can control the mpu with
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the attributes provided in the cortex
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m7 such as shareability cache ability
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etc we will cover them in upcoming
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there are three main reasons that i can
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think of to use the mpu
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the first one is to prevent speculative
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access to the some memory
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locations then we have dma limitations
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and the third is not a reason but we can
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tasks in much better ways let's start
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access speculative access is when cpu
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some memory locations in advance and
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fetches the instructions or data from
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so that the wait cycles can be reduced
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this accessing is done by the cpu on its
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without any provided instruction and it
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helps improve the performance
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but the problem arises when cpu accesses
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that are not available like external
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this could sometimes result in hardware
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fault and we need to prevent this
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speculative access to such locations
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there are 3 types of speculative access
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speculative instruction fetch and
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speculative cache line fills
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speculative read is when the cpu tries
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to read the data in advance from the
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normal memory regions i said normal
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and this is a type of memory regions
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m7 we will cover it in the next video
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anyway cpu tries to read data from this
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even if the data might not be needed it
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so to reduce the weight cycles and
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improve the performance
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but if the memory location is
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unavailable it can cause faults in the
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there you could see errors like this the
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cpu is trying to access a location
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which isn't available we can use mpu to
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block the access to such memory
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here is the memory map of cortex m7 and
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you can see the addresses from 6 million
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to e-million belongs to the external
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these addresses are already available in
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the core irrespective of whether the
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memory is available or not
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so in case we are not using any external
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we must block the access to these
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locations to prevent speculation
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read to external memories next is the
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speculative instruction
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fetch here the cpu fetches the
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instructions in advance
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so to increase the performance but
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sometimes the instruction is not needed
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or sometimes it fetches the instructions
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that aren't even valid
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we could use m-p-u to block the
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instruction access to any location
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and this would prevent cpu to fetch
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instruction from that memory location
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cache line fill means when the processor
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recognizes that an information being
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read from memory is cachable
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the processor reads an entire cache line
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into the appropriate cache slot
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we can make the region not cacheable to
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prevent speculative cache line fill
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that's all about the speculative access
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now let's talk about the second major
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issue and that is d-m-a
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the d-m-a can't work in the cachable
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regions because it needs data coherency
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as of now the hardware support for data
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synchronization is not available in
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we can achieve the coherency using the
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typically by cleaning the cache and
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but an easier way is to use mpu to set
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the region as non-cacheable
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so that the dma can synchronize with cpu
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we will see more about data coherency in
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another thing we can do using mpu is the
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we can restrict any task within certain
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region to prevent its access to other
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this is a good example to understand it
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you can read more about it on the source
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basically here the task a has been
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restricted to the green memory zone
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while the task v is allowed to access
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the entire memory region
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we won't be dealing with this task
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but we will certainly take care of the
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speculative access and the dma
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this is it for the video the next one
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will cover the memory types
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and attributes types in cortex m7
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keep watching and have a nice day ahead
