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Memory Management in STM32 || Cortex M7 || CUBEIDE
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Jun 13, 2021
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View Video Transcript
0:09
hello
0:09
everyone welcome to controllers tech
0:13
as the title says this video will cover
0:16
the memory management in stm32
0:19
this is rather a very long topic so
0:22
there are going to be few more videos on
0:24
it
0:25
by memory management i mean the
0:27
different rams available in stm32
0:30
the external memories like sdram emmc
0:34
etc and also we will see how to use the
0:37
memory protection unit
0:38
aka mpu these videos will be more
0:42
inclined towards the cortex
0:44
m7 processors but you can use the same
0:48
logic
0:48
in any other stm 32 device also
0:52
today we will start with something very
0:55
simple and that is
0:56
how can we use the different internal
0:58
rams to write and read
1:00
data in this video i am going to explain
1:04
a little about different memories in
1:05
cortex m7 processors
1:08
and then we will see how can we use
1:10
these memories to
1:12
save the data or load the data from
1:15
now why is this important well one of
1:19
the main reasons
1:20
is the dma regular dma don't have access
1:24
to the tightly coupled memories
1:26
so we can't read or write data into tcm
1:29
using the dma
1:31
another reason is the large data buffer
1:34
let's say you want to save some picture
1:36
data into the ram
1:38
and if the main memory is not enough we
1:40
can use the other available memories to
1:42
do so
1:44
you will understand this in a while
1:47
let's take a look at the reference
1:52
manual
1:59
this is the system architecture for h745
2:03
series this is as complicated as it can
2:06
get
2:07
and others will be somewhat easier than
2:09
this
2:10
here i have highlighted the internal
2:12
rams that are available
2:19
as you can see there are three different
2:22
domains available
2:23
and each domain we have some memory
2:25
along with other things
2:34
in d2 domain there are three s rams of
2:37
different size
2:41
in d1 domain there is a single axi ram
2:44
of 512 kilobytes
2:50
we have two tightly coupled memories in
2:52
direct contact with the cpu
2:56
and in d3 domain we have 64 kilobytes
3:02
sram
3:06
tightly coupled memories are of two
3:08
types data
3:09
and the instructions
3:13
these memories have zero weight cycle
3:15
for the data processing
3:17
and that's why they are used for the
3:19
real-time operations
3:20
where we can't afford to delay the
3:22
processing
3:24
also only the mdma can access them
3:27
and other dma like dma one or two don't
3:30
have access to these memories
3:37
we have some inter domain buses where
3:40
the data can be accessed between the
3:42
different
3:44
domains
3:47
like t2 to d1 bus where the masters from
3:50
the d2 domain can access the resources
3:52
in the d1 domain
3:59
by masters i mean all these components
4:02
which are placed vertically
4:07
these components can access all these
4:10
resources
4:11
which are placed horizontally
4:17
we also have d1 to d2 bus where the
4:20
masters from d1 domain can access the
4:22
resources from the d2 domain
4:28
similarly there are other buses one
4:31
thing to note here is that there are
4:33
buses d1 to d3
4:35
and d2 to d3 but not in the reverse
4:38
direction
4:38
so the masters from d3 domain can not
4:41
access
4:42
anything other than d3 domain and that
4:45
is the bdma
4:46
it can only access the sram 4.
4:53
you can read more about these buses here
5:01
we will take a look at the dma
5:03
description
5:04
as i said earlier the regular dma cannot
5:07
access the tcm memories and that's what
5:10
it's mentioned here
5:17
this is where the first reason comes up
5:31
here we have the addresses for the
5:36
memories
5:39
dtcm starts at 2 million sram 1
5:43
2 and 3 are part of d2 domain and they
5:46
start at 3 million
5:53
we have axi ram at 2.4 million
6:05
let's take a look at some other mcu to
6:08
understand the difference
6:10
this is the manual for h723 series
6:14
the system architecture looks pretty
6:16
much similar to what we saw in the h745
6:20
series there is some difference between
6:24
the number of srams
6:25
and the size but it's not that of a big
6:32
issue
6:36
now let's see the f76 series
6:45
here the architecture is completely
6:47
different
6:49
it does not have any domains so that's a
6:51
relief
6:53
also it have sram 1 sram 2 and the
6:56
tightly coupled memories
7:00
also note one thing we can access the
7:02
dtcm
7:03
using the ahbs which is basically
7:06
connected to every master
7:08
even the dma1 and dma2
7:16
so i think here we can access the dtcm
7:18
using those dma
7:20
which was not the case with the other
7:22
architectures we saw
7:24
this is very important and you should
7:26
check the architecture of your cpu
7:28
to see if the dma can access these
7:31
memories or not
7:41
here it is mentioned that dma surely do
7:44
have the access to dtcm
7:47
i don't have means to test for the f7
7:49
related queries
7:50
but i will clarify this in the next
7:52
video
7:55
so we saw all the architectures now
7:58
let's see the working
8:02
i have h745 discovery board
8:06
give some name to the project and click
8:10
finish
8:12
let's clear the pin out first i am
8:15
selecting external crystal for the clock
8:20
set up the clock as per your mcu
8:29
this pk 0 is the lcd backlight
8:32
and i like to keep it off
8:42
now in the cortex m7 we will enable the
8:44
instruction
8:45
cache and the data cache enabling the
8:49
cache will improve the performance of
8:50
the mcu by a significant amount
8:53
but this data cache is the source of all
8:55
the issues that we will be handling in
8:57
these videos
8:59
even you know this you should still use
9:01
the cache
9:02
and handle the memory issues the mpu
9:06
part will be covered later
9:08
that's all we need just the basic setup
9:12
i have disabled the m4 core and i am
9:15
only using the m7 for now
9:18
you can check my another video to see
9:20
how to do that
9:22
here at the memory details we can see
9:24
all the types of internal memories
9:26
available to us
9:28
the ram d2 is the total ram in d2 domain
9:31
and it consists of sram 1 2 and 3.
9:35
ram d3 is the ram in d3 domain
9:38
and that is sram 4.
9:43
you can also check these details in the
9:45
flash linker script
9:54
the main ram at 2.4 million and that is
9:57
the axi ram
10:11
now this is where the things get harder
10:14
here i have the linker scripts from the
10:17
other
10:17
mcus this one is for the h735
10:21
and if you see here the main ram starts
10:24
at 2 million
10:32
if you check this address in the manual
10:34
you will find that it's the address for
10:36
the dtcm ram
10:38
this is something we should be worried
10:40
about you will know in a while
10:47
the ram d1 starts at 2.4 million
10:50
and it's the axi ram and other rams are
10:53
as usual
11:08
even in the f-746 the main ram starts at
11:12
2 million
11:24
and that's the address for the dtcm
11:27
again
11:28
now why should we be worried about the
11:30
dtcm being the main ram
11:34
let's see this i am not running the
11:38
second core
11:39
so i will comment out these functions
11:48
let's create a buffer of 1 kilobyte in
11:50
size
11:51
now i will fill this buffer with some
11:54
random data
11:56
let's build it
11:59
also pay attention to the used ram size
12:03
it's increased by 1 kilobyte you can
12:06
also check the memory details
12:08
to know where the buffer is stored
12:13
the buffer is placed at the location
12:15
2002
12:16
c this is not an issue for me but if you
12:19
have the h735
12:21
this address will be in the dtcm ram
12:25
and that's where you need to be careful
12:28
since the dma cannot access dtcm
12:31
you can't perform any operation on this
12:33
buffer using dma
12:35
now we will see how can we change the
12:37
location of this buffer into some other
12:39
ram
12:42
to do this we need to define a section
12:51
we'll call it buffer and put the
12:54
variable along with it
13:00
now we will modify the linker script so
13:02
that this attribute can be pushed into
13:04
some other ram
13:16
here a line one means the data will be
13:18
aligned in 1 byte format
13:21
like here we have 8 byte alignment here
13:24
is 4 bytes
13:26
and now push this to ram d2
13:31
you can see here ram d2 is used by one
13:35
kilobyte
13:39
you can check the memory details to see
13:42
its location
13:43
it's not present in ram anymore and here
13:46
we have it in the d2 ram
13:48
notice that this is at the beginning of
13:50
the d2 ram
13:52
but what if we want to save it at some
13:54
other location inside the d2 ram itself
14:00
we need to modify the linker script
14:02
again
14:03
this time we will use the keyword
14:05
absolute and give the memory location
14:08
here
14:11
we need to assign this location to a
14:13
subsection
14:14
and we will call it tx buffer i am
14:17
creating one more memory location for
14:20
the rx buffer
14:26
it won't show up just yet we need to
14:29
point the variable to that location
14:40
and now if you see we have the tx buff
14:43
in the new memory location
14:49
let's define the rx buffer also
14:59
rx buffer is not showing because we
15:01
aren't performing any action to load the
15:03
data into it
15:09
i want to store different data into the
15:12
tx buffer every time
15:14
and now let's copy the tx buffer into
15:16
the rx buffer
15:20
since we are performing the operations
15:22
on the rx buffer
15:24
it will show up in the d2 ram
15:29
there we have rx buffer in that
15:31
particular memory location
15:33
let's run this program now here i am
15:37
using only one element of the array
15:39
since all of them will have same data
15:41
anyway
15:43
the data is updating every second in
15:45
both the buffers
15:49
let's check the memory locations now
15:55
this is the memory location for the rx
15:57
buffer and you can see the data here
16:06
it's also updating when the new data
16:08
gets copied from the tx buffer
16:17
i will do one more thing here
16:26
this section is for the dtcm ram and
16:29
let's call it buffer dt
16:33
now let's put the rx buffer in this
16:35
location
16:46
so dtcm ram have one kilobyte occupied
16:49
now
17:03
let's run this also we can check the
17:06
memory location of dtcm ram
17:17
here we have the data and it's updating
17:19
properly
17:22
now this is working because cpu can
17:24
access any memory
17:25
so mem copy and memset functions can
17:28
work on any ram
17:30
but it wouldn't have worked if i try to
17:32
copy the data using the dma
17:35
i am stressing too much on dma and there
17:38
is a good reason for it
17:40
most of the peripherals like lcd sd
17:43
card sdram and other will use dma by
17:47
default
17:47
and that's why we need to be prepared
17:49
for those conditions
17:50
where we simply can't use cpu to copy
17:53
the data around
17:55
this was the case for h745 where the
17:58
default ram
17:59
is the axi ram and even if i simply
18:02
create a variable
18:03
it will be created in axiram itself
18:06
but this is not the case for other
18:08
microcontrollers
18:10
i will quickly show an example for f7
18:13
f746
18:20
here i have created a project for f746
18:25
as you can see the main ram starts at 2
18:28
million hexa
18:33
now let's try to simply create an array
18:47
here you can see in the memory details
18:50
the tx buffer is stored in 2028 address
18:55
and if we check the data sheet this is
18:57
the address of the dtcm ram
19:00
now for some application let's so we
19:02
can't have the buffer in dtcm
19:05
so we will store it in the sram 1.
19:11
same method will be used here also
19:26
this is the address where the tx buffer
19:28
will be stored
19:44
here it shows up in the new memory
19:46
location which is the start of the sram
19:49
1.
19:50
this is how we can store the data in the
19:52
different memory locations in the m7
19:54
processors
19:56
this was the introductory video and it
19:58
was an important topic to cover
20:01
in the next video i will cover the dma
20:04
part
20:05
we will see the limitations and the
20:07
solutions
20:09
and later in the series i will cover mpu
20:13
also this is it for the video
20:16
you can download the code form the link
20:19
in the description
20:20
leave comments in case of any doubt
20:24
keep watching and have a nice day ahead
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