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STM32 ADC #9. ADC Hardware Oversampling
Feb 22, 2025
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View Video Transcript
0:01
[Music]
0:09
hello and welcome to controller Tech
0:12
this is the ninth video in the SDM 32
0:15
ADC series and today we will continue
0:18
exploring the ADC peripheral in the
0:21
previous videos of this series we have
0:23
covered how to read single and multiple
0:25
channels of the ADC we have also covered
0:29
the injected conver versions in the
0:30
recent videos of this series today we
0:34
will see how to use the oversampling to
0:36
increase the resolution of the ADC over
0:39
sampling can be incorporated to increase
0:42
ADC resolution past the currently
0:44
available number of
0:46
bits this can help reduce the cost in
0:48
building a system by utilizing lower
0:51
resolution adcs to oversample a signal
0:54
and obtain a higher resolution
0:56
result you can read more about the
0:59
oversampling in the application note a n
1:04
5537 I will just cover some important
1:06
points mentioned in the hardware
1:08
sampling section of this note I have got
1:11
a new device from active firmware
1:14
tools this is a logic analyzer come
1:17
debugger which can be used as an
1:19
oscilloscope and as a firmware debugger
1:22
too I will use this device to generate
1:25
the sinusoidal signal which the SDM 32
1:28
will read
1:30
then the stdm 32 will send the Digital
1:33
Data to this device which will be
1:35
grafted on this device
1:37
itself I am still testing this device
1:40
and once I finish exploring it I will
1:43
make a video about it too I will leave
1:46
the link to the product in the
1:47
description do check it out if you are
1:50
interested I am using nucleo L 496 for
1:54
today's video and here is the connection
1:57
diagram the output pin from the active
2:00
Pro carries the sinusoidal signal and it
2:03
is connected to the pin pa3 of the
2:06
board this is basically the ADC pin this
2:10
output pin is also connected to the
2:12
analog input of the active Pro so that
2:15
we can visualize the sinusoidal signal
2:18
the debugger can be connected using the
2:20
SBI therefore these two pins are used
2:23
for half duplex SBI
2:26
connection all right let's start the
2:28
cube ID and create a new
2:31
project I am using the nucleo L 496
2:34
development board for this
2:36
video my regular boards f103 C8 and F
2:41
446 re do not support the
2:45
oversampling the h750 do support it but
2:49
things are very straightforward in it
2:52
therefore I decided to use this L 496 as
2:55
it will help us understand the topic
2:57
more clearly let's start with the clock
3:01
setup
3:02
first this board does not have an
3:04
external high-speed Crystal so let's use
3:07
the multip speed internal RC oscillator
3:10
itself I will run the system at maximum
3:13
80 mahz clock all right let's enable the
3:17
ADC now I am using the pin pa3 of the
3:21
MCU which is adc1 Channel 8 let's
3:26
configure Channel 8 in single-ended mode
3:30
before we configure this further let's
3:32
go back to the clock
3:34
configuration the ADC is running at 40
3:37
MHz but I need it to run at 64 mahz for
3:40
better explanation of the
3:42
oversampling so let's configure the PLL
3:45
to make it 64
3:47
mahz all right the ADC clock is at 64
3:51
MHz now and if we use the prescaler of
3:54
64 it will come down to 1
3:57
MHz let's configure the resolution to
3:59
bits for now so that we can understand
4:02
the importance of higher resolution
4:04
later I am only using one channel in the
4:07
continuous mode so let's enable The
4:09
Continuous conversion mode we also need
4:13
to enable The dma Continuous request but
4:16
let's configure the dma first here I am
4:19
configuring the dma in the circular mode
4:22
so that the data can be transferred
4:24
continuously note that I am setting the
4:27
data width to half word that is 16 bits
4:30
even though the ADC is configured with 6
4:33
bits
4:33
resolution I am going to change the
4:36
resolution later so this setting will
4:38
remain
4:39
unchanged now enable The dma Continuous
4:43
request we will not configure the over
4:45
sampling for now let's configure the
4:48
sampling time for Channel 8 here is the
4:51
reference Manual of The L4
4:54
96 under the ADC programmable resolution
4:58
you can see the sampling time for
5:00
different
5:01
resolutions for the 6 bits resolution
5:04
the ADC takes 6.5 clock Cycles to
5:07
convert the result now if we use the
5:10
sampling time of 47.5 Cycles the total
5:14
time taken by ADC to sample and convert
5:16
the result would be 54
5:19
micros we will see this on the
5:22
analyzer let's set the sampling time of
5:25
47.5
5:27
Cycles as I mentioned I am using the
5:30
active Pro analyzer and debugger to
5:32
debug this
5:34
application the device can work with the
5:36
SBI so I am configuring the SBI in half
5:39
duplex mode to transmit the data to the
5:42
debugger I am going to use the dma for
5:45
data
5:46
transfer I am also going to toggle a pin
5:50
which will help us measure the ADC
5:51
conversion time therefore the pin pd7 is
5:55
configured in the output mode all right
5:59
that is all the configuration we need so
6:01
click save to generate the
6:04
project let's build the project
6:08
once we will first Define a 16bit
6:11
variable to store the ADC raw data now
6:15
inside the while loop start the ADC in
6:18
the dma mode the converted data will be
6:22
stored in the variable we just defined
6:25
and we are converting only one
6:27
Channel Once the ADC finishes the
6:29
conversion an interrupt will trigger and
6:32
the conversion complete call back will
6:34
be
6:35
called inside this call back we will
6:37
toggle the pin pd7 and then set the
6:40
variable done to one now inside the
6:43
while loop we will check if the variable
6:46
is done is setor one if it is we will
6:50
send the ADC value to the debugger and
6:53
then reset the variable to zero so that
6:56
this Loop can only run when the ADC has
6:58
finished conversion
7:00
all right let's build and Flash the
7:02
project to the
7:04
board this is the software for the
7:06
active Pro debugger and logic
7:09
analyzer this is the output section and
7:12
here I am configuring channel one to
7:14
Output the sine wave I am setting the
7:17
maximum voltage to 1.1 volts so that
7:20
there will be less variation in the
7:24
voltage here you can see the data sent
7:27
by the SDM 32 the the toggling pin pd7
7:31
and at the bottom we have the feedback
7:33
from the active Pro itself let's see the
7:36
toggle time first you can see the pin
7:39
toggles every 54 micros which is exactly
7:43
the same as we
7:44
calculated the maximum voltage is
7:47
reaching around 900 Ms Which is less
7:50
than expected it might be due to some
7:53
wiring issue but let's continue anyway
7:56
now since we are using 6 bits resolution
7:59
there are less number of values
8:01
available for the voltage
8:03
variation therefore you will see this
8:05
line remains horizontal for a lot of the
8:08
time in fact the voltage at this point
8:11
is around 168 Ms whereas it is around
8:15
268 Ms at the end of the horizontal line
8:19
so for almost 100 mols the line remains
8:23
horizontal at the value two similarly
8:27
the line is horizontal for other values
8:29
as well the stm32 reference voltage is
8:33
set to 3.3 volts by default therefore
8:36
for the 1.1 volts the maximum value we
8:39
can get is 1/3 of the maximum value so
8:43
we have seen how in the low resolution
8:45
the ADC is not able to differentiate
8:48
between small voltage
8:50
variation let's configure the resolution
8:52
to 12 bits now we will keep the other
8:56
configurations
8:58
unchanged now now we are using 12bits
9:00
resolution so the conversion time will
9:04
change the ADC takes 12.5 Cycles to
9:08
convert the 12bits
9:10
resolution if we keep the sampling time
9:12
the same as the previous value we should
9:14
now get the result every 60 micros
9:17
seconds let's generate the project again
9:21
we will keep the code unchanged let's
9:24
build and Flash it to the
9:26
board let's run the debugger again
9:30
here you can see the flat lines are gone
9:32
now since there are more values
9:35
available for the ADC it can show
9:37
variation for even small changes in the
9:40
voltage the pin toggling time is 60
9:43
micros which is the same as we
9:47
calculated I have fixed the wiring now
9:49
and here you can see the maximum value
9:52
we are getting is around
9:55
1,350 as I mentioned the SDM 32
9:58
reference voltage is 3.3 Vol by default
10:02
and therefore the input voltage of 1.1
10:04
volts is equivalent to the
10:08
1,365 we are getting almost the same
10:11
value here our curve looks better than
10:14
before now and the ADC values are
10:17
updating as for the analog
10:19
signal now let's imagine I want an even
10:22
higher resolution higher than 12
10:25
bits this is where the oversampling
10:27
comes in here we have the option to
10:30
enable the oversampling so let's enable
10:33
it the oversampling ratio decides how
10:36
many samples we want for each trigger
10:39
let's take a look at the application
10:41
note again this note is specific to SDM
10:44
32 L4 devices but the same logic works
10:48
for all the SDM 32 devices as well there
10:52
are only a few differences and we will
10:54
see them too we know that the number of
10:57
bits increases after over sampling in
11:00
some of the stm32 devices the
11:03
oversampling engine keeps the 16 least
11:06
significant bits after the shifting and
11:08
rounds the result of the removed bits
11:11
the size of the ABC data register in
11:14
such devices is 16 bits therefore a
11:17
higher number cannot be stored into this
11:20
register but devices like the h750 have
11:23
an ADC data register which is 32 bits
11:26
wide therefore we can store even high
11:29
higher resolution results in it we will
11:32
see it at the
11:33
end here in the cube MX you can see the
11:37
oversampling ratio of 32 to 256 is grade
11:41
out let's understand it in the
11:44
application
11:45
note this formula here gives the bit
11:48
depth after the
11:50
oversampling here x represents the bits
11:52
on which the samples are accumulated at
11:55
n represents the oversampling ratio and
11:58
M denotes the bit
12:00
shift for example if we accumulate the
12:03
samples at 12-bit resolution and the
12:06
oversampling ratio is set to 32 without
12:09
any bit shift the resulting resolution
12:11
will be 17
12:13
bits now as I mentioned the a data
12:16
register in L 496 is only 16bit wide
12:20
hence storing 17 bits in the data
12:23
register is not possible therefore we
12:26
need to shift the bit by one which will
12:28
result in 16 bits
12:30
resolution similarly if we use the
12:33
oversampling ratio of 64 it will result
12:36
in 18 bits
12:38
resolution therefore we need to shift
12:41
the bits by two which can result in
12:43
16bits
12:45
resolution as you can see these ratios
12:48
are blocked right now but if we enable
12:51
one bit Shifting the ratio of 32 gets
12:55
unlocked similarly if we enable two bit
12:58
shifting the ratio of 64 gets
13:01
unlocked so without any bot shifting an
13:04
oversampling ratio of two will result in
13:07
13 bits four will result in 14 bits8
13:10
will result in 15 bits and a ratio of 16
13:14
will result in 16
13:19
bits at this moment if I shift the bits
13:22
by four the resolution will be 12 bits
13:25
as shown in the
13:26
calculation but I am keeping it at 16
13:30
bits also note that I am not modifying
13:33
the ADC clock we will first see how it
13:36
works out with this configuration
13:38
itself there are no changes required in
13:41
the code let's build and Flash the
13:43
project to the
13:47
board here you can see now we have the
13:49
maximum values ranging up to 19,500
13:59
let me change the output voltage to 3.3
14:02
volts here and we will capture the data
14:05
again now we are getting the maximum
14:08
values of around
14:10
62,000 this means the resolution is now
14:13
16
14:14
bits you can also observe the curve is
14:17
smoother than before and we have less
14:19
Jitters in the data let's check the ADC
14:23
conversion time the time is around 960
14:28
micros although we were getting 60
14:30
microsc in 12bits
14:33
resolution so what
14:35
happened like I mentioned for the
14:38
oversampling ratio of 16 the ADC will
14:41
take 16 samples for each trigger
14:44
basically the conversion starts as soon
14:46
as the previous conversion is over for a
14:49
single sample the ADC is configured to
14:52
take 60 micros and therefore for 16
14:56
samples it will simply take 16 times the
14:58
more time hence 960
15:02
micros in simple words the oversampling
15:05
by a ratio of 16 reduces the sampling
15:08
frequency by a ratio of
15:11
16 so to maintain the sampling frequency
15:14
at the previous rate we need to either
15:16
increase the ADC clock by 16 times or
15:19
reduce the channel sampling time so that
15:22
the resultant change would be the
15:23
increase in sampling
15:26
frequency I will simply reduce the
15:28
prescaler to increase the ADC
15:31
clock since the oversampling ratio is 16
15:35
I am reducing the prescaler by 16 times
15:38
so that the ADC clock can increase 16
15:41
times all right now we will test the
15:44
project with this
15:46
configuration let's capture the data
15:49
again you can see we still have the
15:51
16bits
15:53
resolution also the pin is toggling
15:56
every 60 micros seconds
15:59
that means we have the same sampling
16:00
frequency which was prior to the
16:04
oversampling let me change the voltage
16:06
back to 1.1 Vols and capture the data
16:09
again we are now getting the maximum
16:12
value of around 19,000 which is near 1/3
16:16
of the maximum 16bit value but note that
16:20
the output data still has Jitters even
16:22
at this
16:23
resolution now this may be due to a lot
16:26
of reasons but I am assuming one of them
16:29
could be the
16:30
resolution we will now see how to use
16:32
even the higher oversampling
16:35
ratio let's open the cube MX again I can
16:39
only reduce the prescaler by a factor of
16:42
four now so I am going to use the
16:45
oversampling ratio of 64 and to do so I
16:49
need to use the bit shift of two this
16:52
will result in a resolution of 16 bits
16:54
again but now we are taking 64 samples
16:57
instead of 16 s
16:59
samples all right let's test the updated
17:02
project again here you can see the
17:05
output data has less Jens now but the
17:08
maximum value is a bit lesser than what
17:10
we were getting
17:11
before it can happen as there are a lot
17:14
of samples being averaged to get these
17:17
values although the resolution is still
17:20
16
17:21
bits also note that the sampling time is
17:24
the same 60 micros
17:27
seconds so we saw how the oversampling
17:29
increases the resolution and it makes
17:32
the output more uniform but it rescues
17:35
the sampling frequency therefore the
17:37
frequency needs to be increased by the
17:40
same factor which is used for the
17:43
oversampling let's take a quick look at
17:45
the reference Manual of the
17:48
h750 here open the ADC register map you
17:53
can see the ADC data register is 32 bits
17:56
in size therefore the over sampler here
17:58
will not have restrictions like we saw
18:00
in case of L
18:03
496 let's check out the over sampler
18:05
section under the ADC functional
18:08
description as mentioned here we can use
18:11
the oversampling ratio from 2 to
18:15
1024 even if we accumulate the
18:17
oversampling results on the 16bit data
18:20
we can reach up to 26 bits resolution
18:22
with the ratio of
18:24
1,24 without any bit shift storing 26
18:29
bits is still possible for the data
18:31
register as it is 32 bits wide we can
18:35
also use the bit shifting to reduce the
18:37
resolution as per our
18:39
requirement the rest of the processing
18:42
will remain the same as we discussed in
18:44
case of L
18:46
496 whatever microcontroller you are
18:48
using it will either have the data
18:50
register 16 bits or 32 bits wide so the
18:55
usage of the over sampler will vary as
18:57
per the width of the data
18:59
register I hope you understood how to
19:01
use the oversampling to increase the
19:04
resolution of the
19:05
ADC this is it for the
19:08
video you can download the project from
19:10
the link in the
19:12
description leave comments in case of
19:14
any doubt keep watching and have a nice
19:18
day ahead
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